1. Field of the Invention
The present invention relates to a method for producing a semiconductor device, and in further detail, it relates to a method for producing a semiconductor device by means of dual damascene process, the device having a multi-layered interconnection structure comprising an organic insulating film, particularly an organic insulating film having a low dielectric constant.
2. Prior Art
With the recent tendency in producing semiconductor devices having finer patterns and multi-layered structure, interconnection delay is found as a serious problem.
More specifically, finer transistors have been implemented thus far in accordance with the scaling law for realizing higher device operation performance. On the other hand, however, this approach has increased the interconnection resistance and the interconnection capacitance, and the interconnection delay expressed by RC is no longer negligible with respect to the operation speed of LSI.
Finer patterns have also increased the current density in the interconnection, and a drop in reliability of the interconnection ascribed to the electromigration as well as an increase in power consumption due to the increase in interconnection capacity is also a severe problem to be overcome.
In order to overcome the aforementioned problems, Cu is being used for the interconnection because it has a lower resistance and a higher electromigration resistance than Al. However, Cu is disadvantageous in that it cannot be processed by a conventional dry etching technique. Accordingly, the application of damascene process using CMP (chemical mechanical polishing) method is widely studied. In particular, a dual damascene process, i.e., a process comprising forming the interconnection and a buried plug of the via holes at the same time, has been recently developed.
For instance, the unexamined published Japanese patent application Hei11(1999)-186391 is proposed a method for producing a semiconductor by employing a dual damascene process as follows.
Firstly, as shown in FIG. 2(a), a first etching stop film 31, a second interlayer insulating film 22, a second etching stop film 32, and a third interlayer insulating film 23 are sequentially formed in this order on a first interlayer insulating film 21 having partially formed therein a buried metallic interconnection 14.
Subsequently, referring to FIG. 2(b), a resist pattern 15 for forming a via hole is formed on the third interlayer insulating film 23, and the second etching stop film 32 as well as the third interlayer insulating film 23 are etched by using the resist pattern 15 as a mask, under etching conditions as such that the etching rate may be the same for the second etching stop film 32 and the third interlayer insulating film 23. At the point etching reaches the second interlayer insulating film 22, the second interlayer insulating film 22 is etched by using the resist pattern 15 as a mask again under the etching conditions as such that the etching rate of the etching stop film 31 should be sufficiently lower than that of the second interlayer insulating film 22.
Then, referring to FIG. 2(c), the first etching stop film 31 that is provided under the second interlayer insulating film 22 is removed by etching, still using the resist pattern 15 as a mask, by changing the etching conditions. A via hole 16 can be formed in this manner.
After stripping off the resist pattern 15, as shown in FIG. 2(d), a resist pattern 17 for forming an interconnection groove is formed on the third interlayer insulating film 23, and the third interlayer insulating film 23 is etched by using the resist pattern 17 as a mask under the etching conditions as such that the etching rate of the second etching stop film 32 should become sufficiently lower than that of the third interlayer insulating film 23. Thus is formed the interconnection groove 18 connected to the first metallic interconnection 14 through the via hole 16.
Subsequently, a metallic film is formed on the entire surface as such that the via hole 16 and the interconnection groove should be completely buried. Then, referring to FIG. 2(e), the metallic film that is provided on the third interlayer insulating film 23 is removed by CMP process to form the metallic interconnection and the connecting plug 19 monolithically inside the interconnection groove 18 and the via hole 16, respectively.
In the process above, however, the via hole 16 is opened after directly forming the resist patterns 15 and 17 on the third interlayer insulating film 23. Thus, in case an organic insulating film having low dielectric constant, which is frequently used in the art to reduce the interconnection capacity, is used for the third interlayer insulating film 23, there occurs a problem that the organic insulating film is also etched on opening the via hole.
More specifically, in the case where a via hole is formed through two or more layers of organic insulating film, i.e., through the third and the second interlayer insulating films, the resist pattern also is gradually etched because the etching rate of the organic insulating film is approximate the same as that of the resist, and the resist pattern suffers thinning gradually as to expose the surface of the third interlayer insulating film. This leads to a problem of causing etching of the third interlayer insulating film before the completion of forming the via hole.
In order to prevent the aforementioned problem from occurring, the resist pattern should be provided sufficiently thick as such not thinner than the film thickness corresponding to the total thickness of the second interlayer insulating film 22 and the third interlayer insulating film 23. However, if the resist pattern is provided too thick, an abnormal pattern formation occurs at the exposure as to cause a novel problem of making incomplete patterning on providing a patterning of a predetermined shape (e.g., in the case of patterning 0.12 μm wide patterns, the upper limit of the resist thickness is about 500 nm).
In the unexamined published Japanese patent application Hei10(1998) -112503 is proposed a technology as follows.
Referring to FIG. 3(a), on a silicon substrate 40 are provided a silicon oxide film 41, an organic insulating film 42 having a low dielectric constant, a silicon oxide film 43 and a resist pattern 44 for forming the interconnection pattern in this order.
Then, as shown in FIG. 3(b), an opening 45 corresponding to an interconnection pattern is provided by dry etching the silicon oxide 43 using the resist pattern 44 as a mask. The resist pattern 44 is removed thereafter.
Referring to FIG. 3(c), subsequently, a resist pattern 46 for forming via holes is formed on the silicon oxide film 43 and the organic insulating film 42 having a low dielectric constant by means of photolithography and etching technique.
Referring to FIG. 3(d), the organic insulating film 42 having a low dielectric constant and the silicon oxide film 41 provided below the opening 45 of the silicon oxide film 43 are selectively and sequentially etched by means of dry etching using the resist pattern 46 as a mask, to thereby providing a via hole 47. The resist pattern 46 is removed thereafter.
Then, referring to FIG. 3(e), an interconnection groove 48 is formed by etching the organic insulating film 42 having a low dielectric constant using the silicon oxide film 43 as a mask, and as shown in FIG. 3(f), an interconnection material is buried in the via hole 47 and the interconnection groove 48 as to establish an interconnection 49.
In accordance with the process above, the via hole 47 is formed by etching using the resist pattern 46 as a mask. In this case, however, the organic insulating film is provided as a single layer. Hence, there is no problem of suffering film thinning and a complete removal of the resist pattern during opening a via hole.
However, to suppress an increase in the interconnection capacity of the resulting semiconductor device, it is desired to use an organic insulating film having a low dielectric constant instead of a silicon oxide film. On the other hand, if an organic insulating film having a low dielectric constant is used in the place of the silicon oxide film 41, the total thickness for the two layers of organic insulating film having a low dielectric constant exceeds the total thickness of the resist pattern 46. Thus, in this case again, there occurs a problem that the surface of the organic insulating film 42 having a low dielectric constant suffers etching.